The present invention relates to flip chip semiconductor packages, and more particularly, to a flip chip semiconductor package in the use of an adhesive larger in contractibility during thermal contraction.
A flip-chip semiconductor package employs advanced packaging technology, which differs from a conventional BGA semiconductor package mainly in that, a semiconductor chip is disposed in the flip-chip semiconductor package in an upside down manner. That is, an active side of the semiconductor chip having a plurality of electronic circuits and electronic elements mounted thereon faces toward a substrate, and is electrically connected to the substrate by a plurality of solder bumps. Then, an underfilling process is performed to underfill gaps between the adjacent solder bumps with an insulative adhesive, for allowing the semiconductor chip to be firmly disposed on the substrate. Such a flip-chip semiconductor package is advantageous with no need of space-occupying bonding wires for providing the electrical connection for the semiconductor chip. This therefore effectively reduces overall thickness of the flip-chip semiconductor package as desired for a low profile demand.
In order to improve both performance and capacity for a single semiconductor package, a substrate can be enlarged in surface area for incorporating more semiconductor chips, or a semiconductor chip can be increased in size for sufficiently accommodating a larger number of electronic elements thereon. However, as shown in FIG. 1, in a solder reflow process for bonding solder bumps 15 and in a cooling process after curing, due to a significant difference in coefficient of thermal expansion (CTE) between a large sized substrate 10 (35xc3x9735 mm2) and a large sized semiconductor chip 11 (15xc3x9715 mm2), the substrate 10 having a relatively greater CTE thermally contracts more rapidly than the chip 11, and accordingly the substrate 10 is warped with its planarity reduced. This further causes the solder bumps 15 to be delaminated or cracked from the substrate 10, and even impedes the adhesive flow in a subsequent underfilling process, thereby possibly resulting in void formation. As such, the reliability concern for the packaged product is greatly increased.
In order to eliminate the above-mentioned drawbacks, U.S. Pat. No. 6,020,221 discloses a fabrication method for preventing substrate warpage from occurrence. As shown in FIG. 2, a stiffener member made of metal such as copper is disposed around the semiconductor chip 11 on the large sized substrate 10, so as to reinforce the resistance of the substrate 10 to thermal contracting stress, and prevent the substrate 10 from deforming in response to the thermal stress in subsequent processes. However, the stiffener member 12 greatly increases the weight of the packaged product, which is not preferable for a low profile demand. Further, the stiffener member 12 is adhered to the substrate 10, and this additional adhering process increases the complexity and cost in fabrication.
Alternatively, U.S. Pat. No. 5,844,319 discloses the use of a collar 13, which has a smaller CTE than that of the substrate 10 and is disposed around the chip 11 on the substrate 10, as shown in FIGS. 3A and 3B. In the solder-reflow process, the collar 13 is used to absorb the difference in thermal stress between the chip 11 and the substrate 10, so as to maintain the planarity of the substrate 10 and protect solder joints 14 from damage, and further allow maintenance or rework to be easily performed for the chip with no need of the underfilling process. However, in no use of the underfilling process, the gaps between the adjacent solder bumps 15 are not blocked by the insulative adhesive, thereby easily resulting in improper electrical contact and short circuit; further, the chip and the substrate may suffer structural cracking and electricity loss in a high temperature process.
A primary objective of the present invention is to provide a flip chip semiconductor package, in which an adhesive compound having a larger coefficient of thermal expansion than that of a substrate is used to form an adhesive dam around a semiconductor chip on the substrate, so as to maintain the substrate planarity and structural intactness of the semiconductor chip. Moreover, the use of the adhesive dam, instead of a metal stiffener member, does not increase the overall weight of semiconductor the package, and eliminates the need of an additional adhering process for disposing the stiffener member, so that fabrication cost can be reduced. In addition, in the flip chip semiconductor package, a gap between the semiconductor chip and the substrate is filled with an insulative adhesive, in an effort to prevent improper electrical contact between adjacent solder bumps, and improve bonding quality of the solder bumps, as well as avoid structural cracking for the semiconductor chip and the substrate in a high temperature environment.
In accordance with the foregoing and other objectives, the present invention proposes a flip-chip semiconductor package, comprising a substrate predefined with a chip bonding area for mounting a semiconductor chip thereon; a larger sized semiconductor chip having its active surface facing toward the substrate and electrically connected to the substrate by a plurality of solder bumps; a dam structure formed around the chip and made of an adhesive compound having larger coefficient of thermal expansion of that of the substrate; an insulative adhesive for filling a gap between the chip and the substrate, and for encapsulating the solder bumps; a plurality of solder balls implanted on a back side of the substrate for electrically connecting the substrate to external devices; and an encapsulant for encapsulating the chip.
Since a conventional solder reflow process is employed for bonding the solder bumps to the substrate, it is not further detailed herein. It is to be noted that, during variation from high to low temperature in the solder reflow process, the substrate deforms more rapidly and to a greater extent than the semiconductor chip, and thus the dam structure needs to have more extensive deformation and produce a greater contraction force for counteracting excessive thermal stress of the substrate. As the result, planarity and structural intactness can be well maintained for the substrate and the semiconductor chip, as well as bonding quality of the solder bumps can be assured. Compared to a conventional metal stiffener member for increasing resistance for a substrate to thermal stress, the dam structure of the invention not only reduces overall weight of the semiconductor package, but also eliminates the need of an additional adhering process for use with the metal stiffener member, so that the fabrication cost can be reduced.
Moreover, gaps between the adjacent solder bumps are filled with the insulative adhesive by using a conventional dispensing process; this can prevent the adjacent solder bumps from electrically coming into contact with each other, and also help dissipate thermal stress between the substrate and the semiconductor chip. Therefore, bonding reliability of the solder bumps can be assured, and the substrate and the semiconductor chip can be prevented from structurally cracking at a high temperature in subsequent fabrication processes.